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The CX6800 Hybrid ASIC is a combination of Standard Cells & Structured ASIC technologies and based on 0.13µ technology. The CX6800 uses up to 8 layers of programmable metal, and supports performance levels up to 300MHz. This Hybrid ASIC has up to 5M usable gates and embedded memory. This product is ideal for cost-effective solutions for designs with 1.2V cores, 1.8V/2.5V/3.3V I/O, USB 2.0 Phy, PCIe Phy and other IP. The CX6800 enables cost reduction of expensive FPGA’s, mid to high volume, and fast turnaround for computing, consumer, networking, and industrial markets. |
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| Specifications | |
|---|---|
| Process | 0.13μ |
| Usable Gates (K) | 5M |
| Maximum Pads | Based on Customer Requirements |
| Max System Clock [MHz] | 300 |
| Core Voltage | 1.2V |
| Memory | Based on Customer Requirement |
| Embedded Hard Macro IP | Can include any Mixed-Signal IP |
| Family | CX6800 |
| Datasheet | Datasheet |
| Status | Production |